In a conventional semiconductor integrated circuit design, the register transfer level (RTL) which describes behaviors of registers and combined circuits between registers included in a circuit is designed using hardware description language.
The circuit scale of the integrated circuit has been increased in recent years, which takes large amount of time to design RTL, resulting in a problem.
Then, a high level synthesis technique which generates automatically RTL using C language, C++ language, System C language, and so on that are high level language of which the level of abstraction is higher than RTL are proposed, and a high level synthesis tool implementing the same is commercially available.
Patent Literature 1 discloses that, as a pre-processing of input to the high level synthesis tool, in order to eliminate redundant memories, array description part which may cause generation of redundant memories is detected, and the array is automatically deleted, thereby obtaining an integrated circuit with a small circuit scale.